17th International Parallel Tools Workshop, Dresden

Oct 1, 2026, 9:00 AM → Oct 2, 2026, 1:00 PM Europe/Berlin

APB Andreas-Pfitzmann-Bau, E023 (01187 Dresden)

Bert Wesarg (TU Dresden), Hartmut Mix (TU Dresden)

October 1–2, 2026

The International Parallel Tools Workshop is a platform for developers and users to exchange the latest trends and advances in tools for High Performance Computing applications. 

The workshop series is a joint event between HLRS Stuttgart and ZIH Dresden. In 2026 the workshop will once again take place at TU Dresden.

Participants can expect presentations on the state-of-the-art of parallel programming tools, ranging from debugging tools, performance analysis and best practices in integrated developing environments for HPC platforms.

Conference website

 

https://tu-dresden.de/zih/tools_workshop_2026 (Contact: Dr. Hartmut Mix, Bert Wesarg)

 

 

Registration

 

Graduated pricing (incl. VAT)

Speaker: €120.00

Academic: Early €120.00 (until 2026-09-03) / Late €170.00 (after 2026-09-03)

Others: Early €250.00 (until 2026-09-03) / Late €300.00 (after 2026-09-03)

After registering for the workshop, you will receive an invoice (by e-mail). Sending the invoice will take some time as it is processed centrally by TU Dresden.

The contribution will be collected by the local organizer to cover the costs of hosting the workshop. 

 

Hotel contingents
 

B&B HOTEL Dresden-City-Sued, Bamberger Str.14, 01187 Dresden 

• 1 or 2 nights, 2026-09-30 till 2026-10-02
• Night in a single room: €72.55 per room
• including breakfast + plus local accommodation tax (6 % of the accommodation rate per person and night in the room)
• Parking: €12.00 per car / night in the hotel's underground car park

The rooms can be booked until 2026-09-09 with the keyword "Tools" via e-mail or telephone (dresden-city-sued@hotelbb.com, +49 6146 815354-6). Each booked room can be cancelled free of charge up to 1 day before arrival.
https://www.hotel-bb.com/de/hotel/dresden-city-sued

For organizational questions, please contact Diana Häsener (zih-veranstaltungen@tu-dresden.de). For all other questions, please contact us at tools@zih.tu-dresden.de .

Thu, October 1

1 Welcome

Session 1

2 Performance-Aware Software Engineering: Utilizing Analysis Tools in the Development Workflow of Aerospace Applications

This presentation provides an overview of the use of tools for verifying parallel performance and correctness at the DLR institute in Dresden.
Typical use cases, examples of identified bottlenecks and their performance impact as well as problems uncovered are shown for both individual and coupled applications.
Additionally, automated builds are demonstrated for coupled problems involving deep dependency stacks, ranging from non-instrumented stacks through builds with just one instrumented library to fully instrumented software stacks.

3 A Diagnostic Tool for Phase-Aware Resource Allocation in Malleable HPC Workloads

As these systems become larger and more complex, managing efficient utilization of resources becomes increasingly challenging.
While de-facto job schedulers such as Slurm and Flux improve resource utilization at various levels, for example by enabling job concurrency, the traditional static allocation of computational resources at job start compels users to provision for peak demand across all phases for the application, contributing to resource under-utilization.
At the same time, user workloads are increasingly dynamic, consisting of multiple distinct execution phases, each demanding different resource configurations.
Such workloads are no longer rigid, with a fixed resource allocation request, but malleable, facilitated by dynamic resource allocation.
In principle, dynamic resource allocation can boost both per-job utilization and cluster throughput; however, the gains depend on the workload and on the scheduler allocation scheduling latencies, and realizing them requires further tuning of resource change requests, e.g., which phases to resize, by how much, and when, so that each change takes effect in time to cover resource acquisition, synchronization, and data redistribution. In current practice, users rarely have this knowledge a priori.

We present a phase-aware diagnostic tool on top of FlexiAlloc, a dynamic resource management framework, to support fine-grained scheduling for better utilization via successive feedback loops.
It fuses the scheduling records with resource utilization telemetry, and correlates a job's allocation requests with observed usage (e.g., CPU, memory) on a shared timeline.
With that, the tool enables users to analyze whether their phase-targeted resource change requests were effective.
By including the tool in the scheduling workflow, it enables automatic incremental resource scaling experiments for building an evolving performance model for phase-aware allocation in later runs, ultimately assisting the scheduler to insert requests automatically via agents

4 Towards Transparent Continuous Performance Monitoring in HPC Systems through Batch System Integration

The increasing cost of new HPC systems and a growing demand for computing resources require existing systems to be operated for longer periods and at higher utilization levels. Consequently, efficient use of available resources is becoming increasingly important. While system-side optimizations such as improved scheduling and reduced downtime contribute to higher throughput, continuous analysis and optimization of
application performance remain essential.

In this work, we present an approach that transforms continuous performance monitoring from a user-initiated activity into a transparent infrastructure service of the batch system. We integrate the lightweight Linux performance analysis tool lo2s into the Slurm Workload Manager using a SPANK plugin. This integration enables transparent monitoring
throughout the job lifecycle without requiring modifications to existing user workflows.

Due to its low overhead and support for a broad range of hardware and software metrics, lo2s is well suited for continuous monitoring in production environments. Its process-centric and system-monitoring modes enable both detailed analysis of individual applications and system-wide observation of resource utilization.

A prerequisite for this is the continuous collection of performance characteristics of production applications in the context of their system environment. However, existing performance analysis tools are typically explicitly launched by users, may have high overhead and are therefore not or only partially suited for automated, system-wide performance monitoring.

We describe the architecture and implementation of the plugin, discuss security aspects and limitations, show achievable low overhead, and demonstrate how continuous performance monitoring can support both system operators and users in understanding and optimizing HPC workloads.

12:00 PM Lunch Break (TU Mensa)

Session 2

5 Extended Visualization and Analysis of Non-Blocking Multi-Threaded Communication of a Large-Scale CFD Solver with Vampir

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6 Combining PyTorch Instrumentation APIs with Existing HPC Analysis Tools

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2:30 PM Coffee Break

Session 3

7 Unified CPU and GPU sampling with the TAU Performance System

Performance analysis tools provide profiling and tracing capabilities that help developers understand the behavior of their applications.
However, instrumenting only the entry and exit points of functions may not provide sufficient information to correctly identify performance bottlenecks.
A function may contain hundreds of lines of code, multiple nested loops, or regions that may not be easy to manually instrument.

To obtain finer-grained performance information, performance analysis tools can periodically inspect the execution state of an application through sampling.
Sampling can capture information about the currently executing code, such as source locations, executed instructions, and, when supported, stall events and their causes.

We have extended the TAU Performance System to support sampling on both CPUs and GPUs. GPU sampling is supported on NVIDIA, AMD and Intel hardware.
On NVIDIA GPUs, both sampling and stall events are generally available.
On AMD GPUs, sampling is supported on modern devices, but stall events are currently limited to the MI300 and MI350 series. On Intel GPUs, both sampling and stall events are supported only on recent GPU architectures (Data Center GPUs and newer generations).

This extension of the TAU Performance System provides a unified performance analysis tool across heterogeneous CPU-GPU systems on modern HPC platforms.

8 libgOMPT: Enabling OMPT for libgomp

The OpenMP Tools Interface (OMPT) provides a standardized mechanism for performance analysis and tooling, enabling developers to gain detailed insight into OpenMP program execution. While the LLVM OpenMP runtime provides a mature OMPT implementation, libgomp has no support at the moment, limiting the availability of performance tools on GCC compiled code.

This talk presents our work to add OMPT support in libgomp. We describe the implementation of the core OMPT infrastructure, including the general callback interface, the general OMPT API entry points, and support for device callbacks. The implemented functionality substantially improves compatibility with existing OMPT-based tools and brings libgomp much closer to a complete implementation of the specification. We will discuss the tool compatibility and limitation based on Score-P and Archer as examples.

Beyond the implementation itself, we will discuss the performance implications of enabling OMPT based on the EPCC benchmark suite. Additionally, we will speak about architectural changes proposed for upstream libgomp. In particular, we will motivate the partial conversion of the runtime to C++ to leverage templating code with and without OMPT enabled, and we introduce additional internal runtime API entry points required to expose events that are not currently observable through libgomp's existing interfaces. We will conclude with some insights about the upstreaming effort.

7:00 PM Evening Dinner

Fri, October 2

Session 4

9 Automated Metadata Collection, Standardization, and FAIR Publication of HPC Performance Data in NFDIxCS

Traces and profiles produced by HPC tools such as Score-P and CUBE are essential for performance analysis and optimization. However, these datasets are rarely shared in a reusable form because important contextual information is often missing. Details about the hardware, software environment, application configuration, and scheduler settings are required to interpret and reproduce an experiment. Within Task Area I3 of NFDIxCS, the German National Research Data Infrastructure for and with Computer Science, we are developing tools and services for the FAIR management of HPC performance data that address these challenges throughout the entire workflow, from executing an experiment to publishing its results.

Automated Metadata Collection

Metaper is an open-source Python command-line tool that automatically captures metadata on HPC systems. It collects information about job allocation, hardware, software, and the execution environment with minimal user interaction. Tool-specific plugins can enrich the collected metadata and add preprocessing results. A post-job finalization step incorporates scheduler accounting data that becomes available only after the job has completed. The resulting metadata is stored in a machine-readable format based on a standardized schema for representing HPC performance analyses.

Publication and Reuse

Perfortal is a web-based platform for publishing and sharing performance datasets. Metadata generated by Metaper can be imported to pre-fill submission forms, reducing manual effort while allowing users to add project-specific information and additional results. By using a shared metadata schema, both tools provide a consistent workflow.

Towards RDMC-Based Research Objects

We further discuss how this workflow can be integrated into the Research Data Management Container (RDMC) concept of NFDIxCS. RDMCs aim to combine data, metadata, software, and the execution environment into reusable research objects. Automated metadata collection and the publication workflow reduce the effort required to generate such containers and improve reproducibility across HPC systems and performance analysis tools.

Our approach aims to lower the barriers to sharing performance data, improve reproducibility, and support the reuse of performance experiments by providing standardized metadata and publication mechanisms. We invite discussion on metadata standards, the integration of performance analysis tools, and workflows for FAIR research data management.

10 Checkpoint-Based State Comparison for Localizing Correctness Regressions in Scientific Codes

Performance optimization of scientific and high-performance computing (HPC) applications frequently introduces subtle behavioral changes that go unnoticed until they manifest as incorrect scientific results. Detecting whether such changes alter computed state, and precisely where in the code and iteration space a divergence first occurs, remains a largely manual and time-consuming process.
Existing tools address related but distinct problems: numerical debuggers (e.g., FPChecker) quantify rounding-error propagation within a single run rather than comparing two executions against each other; record-and-replay debuggers (e.g., rr) provide deterministic replay but no notion of application-level checkpoints or domain-specific state; interactive differential debuggers such as IDD run a baseline and a regressed executable side by side under a pair of synchronized gdb/lldb sessions for the full comparison session, incurring continuous debugger-control overhead, and rely on the developer to manually drive both sessions and issue comparison commands rather than on automated, source-level state checkpoints; and offline diffing tools (e.g., h5diff) compare dumped output after the fact, without runtime or debugger integration.
In this work, we present a lightweight framework for checkpoint-based state comparison in scientific applications. Developers annotate variables of interest directly in source code with domain-meaningful, multi-dimensional context (e.g., time step, sub-iteration, MPI rank) through an explicit API. A reference run records these states; subsequent, independent runs execute at native speed and compare against the reference and, on the first detected mismatch, provide location information or halt directly into an attached debugger at the exact point of divergence - without requiring the two executions to run simultaneously, continuous dual debugger sessions, or interactive command-driven comparison.
Different methods for comparison are provided based on the type of data as well as the acceptable memory overhead, ranging from low-overhead hash-based testing up to full data set comparisons using configurable floating-point tolerances. We describe the design and implementation of our framework and demonstrate its use in localizing correctness regressions.

11 Parallel Scalability Analysis of a Hierarchical Adaptive Mesh Refinement Workflow

Computational fluid dynamics underpins aerospace development. However, accurate simulation of full aircraft configurations at in-flight speeds requires large grids and, hence, massive parallelism on high performance computers. For such applications, adaptive mesh refinement (AMR) allows to lower the computational effort by refining the mesh at locations of interest. As this happens during the simulation process, performance and scalability of the overall toolchain is tightly coupled with the scalability of the AMR library, the flow solver and the coupling between them.

This contribution employs the performance tools Score-P, Cube and Vampir to investigate and improve the scalability of a simulation toolchain using AMR: A small Python-steered toolchain implemented within the FlowSimulator framework, coupling the flow solver "CFD by ONERA, DLR and Airbus" (CODA) with the hierarchical AMR library FSAdaptationNG which was just extended towards MPI parallelism. With the performance tools, it is demonstrated that CODA scales well even down to a few hundred cells per core, whereas FSAdaptationNG's initial MPI implementation scales less well. Using the performance tools' profiling and tracing, the underlying performance bottlenecks - ranging from unrequired synchronization over serial code parts to load imbalance - are identified and thereafter solutions proposed and first performance gains shown. The study demonstrates how parallel analysis tools can expose and fix scalability bugs not just in academic, but also industrial applications and how a tailored repartitioning strategy optimizes the overall runtime of the coupled workflow. After showcasing the usage of the benefits of the performance tools, effectivity, usability, and ease-of-use of them for such applications is discussed.

10:30 AM Coffee Break

Session 5

12 Assessing CPU Code Quality

Code quality is essential for getting high performance: for various reasons (poor performance models, lack of adequate transformations, limited analysis capabilities …) compilers are often producing suboptimal codes, which can significantly hurt performance.

MAQAO is a performance analysis framework offering features designed for assessing CPU (X86 and ARM) code quality, detecting potential compiler “mistakes” and suggesting workarounds (inserting compiler flags, rewriting loops, …).

In our presentation, we will first demonstrate MAQAO capabilities to assess code quality and detail strategies to make comparative studies between different compilers and compiler settings. Then we will show how these comparative studies can be used to “transfer” optimizations between compilers. These MAQAO capabilities will be illustrated through real code examples.

13 WINIC: An Automatic Cycle-Accurate Multi-Platform Microbenchmarking Tool for Instruction Performance Metrics

Performance models allow developers to gain important insights into the interaction of their code with the hardware that executes it, and enable them to apply target-specific optimizations. To create in-core performance models for out-of-order processors, architecture-specific performance metrics like latency, throughput, and port binding of individual instructions are indispensable. For x86 microarchitectures, there already exist tools to automatically obtain those values; however, the extension of performance modeling tools like the Open Source Architecture Code Analyzer (OSACA) to support further architectures like RISC-V emphasizes the need for a cross-platform microbenchmarking tool.
We present WINIC (What I Need Is Cycles), an automatic cross-platform microbenchmarking tool. Unlike previous tools, it can obtain throughput and operand-based latency metrics for most supported instructions of any 64-bit x86, AArch64, and RISC-V microarchitecture without the need for root permissions or extended system control levels.
We cover the methodology of microbenchmarking and the approach of WINIC to collect cycle-accurate performance data for assembly instructions.
We show that WINIC can be used to automatically obtain a vast number of accurate results for x86, AArch64, and RISC-V microarchitectures.
We show for four target microarchitectures that its results match between 70% and 97% of the performance data of non-memory instructions obtained by similar tools and documentation and WINIC is able to accurately measure throughput and latency metrics for instructions with memory access in L1 cache.
Furthermore, we show how operand-dependent latencies in between instruction operands measured by WINIC can be used to improve the in-core performance predictions on selected micro-kernels, exemplarily for the Neoverse V2 microarchitecture.

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14 Closing remarks